Semiconductor logic circuit devices are shipped through three steps, i.e., a design step, a production step and a test step. Here, a test is to apply a test vector upon a manufactured semiconductor logic circuit device, to observe a test response from the semiconductor logic circuit device, and to compare the test response with an expected test response, thus determining whether the semiconductor logic circuit device is good or defective. The rate of good semiconductor logic circuit devices is called a manufacturing yield which would remarkably affect the semiconductor logic circuit devices in quality, reliability and manufacturing cost.
Generally, a semiconductor logic circuit device (mainly, a sequential circuit) is constructed by a combinational portion formed by logic elements such as AND (AND) gates, NAND (NAND) gates, OR (OR) gates and NOR (NOR) gates, and flip-flops storing an internal state of the circuit. In this case, the combinational portion has external input lines (PI), pseudo external input lines (PPI) serving as output lines of the flip-flops, external output lines (PO), and pseudo external output lines (PPO) serving as input lines of the flip-flops. Inputs to the combinational portion are ones supplied directly from the external input lines and ones supplied by the pseudo external input lines. Also, outputs from the combinational portion are ones appearing directly at the external output lines and ones appearing at the pseudo external output lines.
In order to test the combinational portion of a semiconductor logic circuit device, a predetermined test vector is required to be applied thereto from the external input lines and the pseudo external input lines of the combinational portion, and a test response is required to be observed from the external output lines and the pseudo external output lines of the combinational portion. Here, one test vector is formed by bits corresponding to the external input lines and the pseudo external input lines. Also, one test response is formed by bits corresponding to the external output lines and the pseudo external output lines.
However, it is generally impossible to directly access the output lines of the flip-flops (the pseudo external input lines) and the input lines of the flip-flops (the pseudo external output lines) in the semiconductor logic circuit device from the exterior. Therefore, in order to test the combinational portion, there are problems in the controllability of the pseudo external input lines and the observableness of the pseudo external output lines.
A scan design is a technique for solving the problems of controllability and observableness in the test of the combinational portion. Such a scan design is to replace the flip-flops with scan flip-flops by which one or a plurality of scan chains are formed. The scan flip-flops are controlled by a scan enable (SE) signal. For example, when the scan enable (SE) signal is at logic value 0, the scan flip-flops carry out the same operation as conventional flip-flops, so that, if a clock pulse is given, the output values of the scan flip-flops are renewed by the combinational portion. On the other hand, when the scan enable (SE) signal is at logic value 1, the scan flip-flops with the other scan flip-flops within the same scan chain form one shift register, so that, if a clock pulse is given, new values are shifted from the exterior in the scan flip-flops, and simultaneously, values which have been in the scan flip-flops are shifted out to the exterior. Generally, scan flip-flops in the same scan chain share the same scan enable (SE) signal; however, scan enable (SE) signals in different scan chains may be the same or different from each other.
A test for a scan-designed semiconductor logic circuit device is carried out by repeating shift operations and capture operations. A shift operation is carried out in a shift mode where the scan enable (SE) signal is at logic value 1. In the shift operation, one or a plurality of new values given from the exterior are shifted in the scan flip-flops within the scan chain. Also, simultaneously, one or a plurality of values which have been located in the scan flip-flops within the scan chain are shifted out to the exterior. A capture operation is carried out in a capture mode where the scan enable (SE) signal is at logic value 0. In the capture mode, one clock pulse is simultaneously given to all the scan flip-flops in one scan chain, so that the values of the pseudo external output lines of the combinational portion are taken into all the scan flip-flops.
A shift operation is used for applying a test vector to the combinational portion through the pseudo external input lines and for observing a test vector from the combinational portion through the pseudo external output lines. Also, a capture operation is used for taking a test response of the combinational portion in the scan flip-flops. Shift operations and capture operations are repeated upon all test vectors, thus testing the combinational portion. Such a test method is called a scan test method.
In a scan test method, application of a test vector to the combinational portion is formed by a portion applied directly from the exterior inputs and a portion applied by shift operations. Since an arbitrary logic value is set in an arbitrary scan flip-flop, the problem of controllability of the pseudo external input lines is solved. Observation of a test response from the combinational portion is formed by a portion carried out directly from the external output lines and a portion carried out by shift operations. Since an output value of an arbitrary scan flip-flop can be observed by shift operations, the problem of observableness of the pseudo external input lines is solved. Thus, in a scan test method, it is only necessary to obtain a test vector and an expected test response for the combinational portion by using an automatic test pattern generation (ATPG) program.
Despite the effectiveness of the above-mentioned scan test method, there is a problem in that the power consumption is remarkably larger in a test mode than in a usual operation mode. For example, if the semiconductor logic circuit device is constructed by CMOS circuits, the power consumption consists of static power consumption due to leakage currents and dynamic power consumption due to switching operations of the logic gates and the flip-flops. Additionally, the latter dynamic power consumption consists of shift power consumption in shift operations and capture power consumption in capture operations.
Generally, a large number of clock pulses are required for one test vector in shift operations. For example, in order to set new values in all the scan flip-flops of a scan chain, a number of clock pulses corresponding to the number of the scan flip-flops are required at most. As a result, the shift power consumption is increased to induce excessive heat. Therefore, semiconductor logic circuit devices would be damaged. Various techniques for decreasing the shift power consumption have been vigorously developed.
On the one hand, generally, a single clock pulse per one scan chain is required for one test vector in a capture operation. Therefore, heat by the capture operation mode creates no problem. However, in a capture mode, when a test response of the combinational portion appearing at the pseudo external output lines is taken in the scan flip-flops, if the values of the test response are different from the current values of the scan flip-flops, the values of the corresponding scan flip-flops change. If the number of the scan flip-flops whose output values have changed, the power supply voltage is instantaneously changed by the switching operation of the logic gates and the scan flip-flops. This is also called an IR (I: current and R: resistance) drop phenomenon. The IR drop phenomenon would erroneously operate the circuit so as to take erroneous test response values in the scan flip-flops. Thus, even semiconductor logic circuit devices normally operable in a usual state would be deemed to be defective in a test state, which can be an erroneous test. As a result, the manufacturing yield would be decreased. Particularly, when semiconductor logic circuit devices become ultra-large in scale, more fine-structured and lower in power supply voltage, the manufacturing yield caused by the erroneous test would be remarkably decreased. Therefore, it is essential to decrease the capture power consumption.
When a single clock signal is used in a test mode, the capture power consumption can be decreased by a clock gating technique; however, this would remarkably affect the physical design of semiconductor logic circuit devices. Also, when multiple clock signals are used in a test mode, the capture power consumption can be decreased by a one hot technique or a multiple clock technique; however, the former technique would remarkably increase test data amount, and the latter technique would require enormous memory consumption in generating test vectors which is a large burden to an ATPG program. Therefore, in view of the decrease of the capture power consumption, it is expected to decrease the impact to the physical design, to suppress the increase of test data amount and to decrease the burden of an ATPG program.
On the other hand, many test cubes, i.e., input vectors with unspecified bits (hereinafter, referred to as X-bits) are usually generated in a process for generating test vectors using an ATPG program. Also, when a set of test vectors without X-bits are given, some bits of some test vectors can be converted into X-bits without changing the fault detection rate of the set of test vectors. That is, test cubes can be obtained by an X-bit extracting program. The reason for the existence of test cubes is mainly to have only to set necessary logic values in a part of bits of the external input lines and the pseudo external input lines in order to detect one target fault in the combinational portion. Since assignment of 0's or 1's to the remainder bits does not affect the detection of the target fault, such remainder bits are X-bits for the target fault.
A test cube with X-bits is strictly an intermediate product appearing in a process for generating a test cube without X-bits. Therefore, logic values (0 or 1) finally have to be filled into the X-bits of the test cube in an appropriate method, i.e., an algorithm filling method, a merge filling method or a random filling method.
The algorithm filling method determines and fills optimum logic values (0 or 1) for the X-bits in a test cube in an algorithm in order to obtain an object. Such an algorithm is often mounted on an ATPG program. This algorithm filling method is used for decreasing the total number of test vectors in dynamic compaction (see: non-patent documents 1 and 2) or for decreasing the shift power consumption (see: non-patent document 3).
When a test cube is merged with another test cube, the merge filling method fills 0 or 1 in X-bits of the test cubes so that a bit of the test cube has the same logic value as its corresponding bit of the other test cube. For example, in order to merge a test cube 1X0 with a test cube 11X, 1 is assigned to the X-bit of the test cube 1X0 and 0 is assigned to the X-bit of the test cube 11X. This merge filling method is used for decreasing the total number of test vectors in static compaction (see: non-patent document 1) or for decreasing the shift power consumption (see: non-patent document 4).
The random filling method assigns 0 or 1 randomly to X-bits in a test cube. This random filling method is often carried out for remaining X-bits after the algorithm filling method or the merge filling method is carried out. This random filling method is used for decreasing the total number of test vectors in dynamic compaction (see: non-patent document 1) or for decreasing the shift power consumption (see: non-patent document 4).    Non-patent document 1: M. Abramovici, M. Breuer, and A. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, pp. 245-246., 1990.    Non-patent document 2: X. Lin, J. Rajski, I. Pomeranz, S. M. Reddy, “On Static Test Compaction and Test Pattern Ordering for Scan Designs”, Proc. Intl. Test Conf., pp. 1088-1097, 2001.    Non-patent document 3: S. Kajihara, K. Ishida, and K. Miyase, “Test Vector Modification for Power Reduction during Scan Testing”, Proc. VLSI Test Symp., pp. 160-165, 2002.    Non-patent document 4: R. Sankaralingam, R. Oruganti, and N. Touba, “Static Compaction Techniques to Control Scan Vector Power Dissipation”, Proc. VLSI Test Symp., pp. 35-40, 2000.